1. Field of the Invention
The present invention relates to an image segmentation apparatus for image processing, which recognizes an image or detects movement in real time, an image segmentation method, and an image segmentation integrated circuit.
2. Description of the Related Art
In image segmentation, individual objects (e.g., mobile objects such as a human face and car) are taken from a complicated natural image taken as an input, and this processing is basic and indispensable for performing image processing which is object-based processing, such as image recognition and movement detection.
Various image segmentation methods have heretofore been proposed, and these methods are roughly classified into:                (1) a method based on a contour line [see Documents 7, 8, for example];        (2) a method based on a region [see Document 7, for example]; and        (3) a method in which both (1) and (2) are combined [see Document 7, for example] or a method of formulating a combined optimization problem [see Document 1, for example].        
However, processing in software is assumed in an image segmentation method with respect to a color or gray scale value, which has heretofore been proposed. Therefore, since complicated processing is required, the time required for the processing is long. Since the algorithm is complicated, it is difficult to realize the algorithm in a small area such as hardware, and it is difficult to process the image in real time (about several msec). Furthermore, various exclusive-use algorithms are required for segmenting a natural color or gray scale image. To realize the real-time processing, hardware acceleration is indispensable.
Additionally, in recent years, there has been a rising demand for an image recognition technique in order to realize an intellectual information processing technique. Especially, it is necessary to process visual information (information on a natural image) taken from a camera or the like in realizing an intelligent robot which operates or makes decisions like a human or in recognizing faces or mobile objects in real time. Since the amount of visual information is generally enormous, a considerably long processing time is required for the processing with a general-purpose computer or the like. In the control of the robot and the image recognition, a demand for a processing rate of the visual information becomes severe, and high-speed processing in real time is required.
Therefore, in recent years, to deal with the image processing in which the real-time processing is indispensable, such as the control of the intelligent robot and the recognition of the mobile object, various image segmentation algorithms [see Documents 4, 7, 9, for example] and an image segmentation circuit by hardware for the real-time processing [see Documents 2, 3, 5, 6, for example] have been intensively researched.
However, in a conventional integrated circuit realized as hardware, since a high-speed property is regarded as important, there is a problem that power consumption or chip area increases. Therefore, it has been difficult to realize an image segmentation circuit with respect to a large image size from viewpoints of the power consumption and chip area.
[Document 1] S. M. Bhandarkar and H. Zhang, “Image segmentation using evolutionary computation”, IEEE Trans. on Evolutionary Computation, Vol. 3, No. 1, (1999).
[Document 2] H. Ando, T. Morie, M. Nagata, and A. Iwata, “A nonlinear oscillator network for gray-level image segmentation and PWM/PPM circuits for its VLSI implementation”, IEICE Transactions on Fundamentals, E83-A(2), pp. 329 to 336, 2000.
[Document 3] H. Ando, T. Morie, M. Miyake, M. Nagata, and A. Iwata, “Image segmentation/extraction using nonlinear cellular networks and their VLSI implementation using pulse-modulation techniques”, IEICE Transactions on Fundamentals, E85-A(2), pp. 381 to 388, 2002.
[Document 4] T. Koide, T. Morimoto, Y. Harada, and H. J. Mattausch, “Digital gray-scale/color image-segmentation architecture for cell-network-based real-time applications”, In Proceedings of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2002), pp. 670 to 673, 2002.
[Document 5] T. Morimoto, Y. Harada, T. Koide, and H. J. Mattausch, “Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation”, In Proceedings of 2002 IEEE Asia-Pacific Conference on ASICs (AP-ASIC2002), pp. 237 to 240, 2002.
[Document 6] T. Morimoto, Y. Harada, T. Koide, and H. J. Mattausch, “Low-complexity, highly-parallel color motion-picture segmentation architecture for compact digital CMOS implementation”, In Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM2002), pp. 242 to 243, 2002.
[Document 7] J. C. Russ, “The Image Processing Handbook”, pp. 371 to 429, CRC PRESS, 1999.
[Document 8] S. Sarkar and K. L. Boyer, “Integration inference, and management of spatial information using Bayesian networks: Perceptual organization”, IEEE Transactions on Pattern Analysis and Machine Intelligence, 15(3), pp. 256 to 274, 1993.
[Document 9] D. L. Wang and D. Terman, “Image segmentation based on oscillator correlation”, Neural Computation, 9(4), pp. 805 to 836, 1997.
[Document 10] Jpn. Pat. Appln. KOKAI Publication No. 2003-346142, “Image Segmentation Method, Image Segmentation Apparatus, Real-Time Image Processing Method, Real-Time Image Processing Apparatus, and Image Processing Integrated Circuit”.